The subject matter of the present application relates to the packaging of a microelectronic element and related circuitry, for example, a method of making a structure. More particularly, the subject matter of the present application relates to an integrated circuit structure including a through-silicon via (TSV) and methods of its manufacture.
A microelectronic device, such as a semiconductor chip, typically requires many input and output connections to other electronic components. The input and output contacts of a semiconductor chip, or a comparable device, are generally disposed in grid-like patterns that substantially cover a surface of the device (commonly referred to as an “area array”) or in elongated rows that may extend parallel to and adjacent to each edge of the device's front surface or in the center of the front surface. Typically, devices such as chips must be physically mounted on a substrate such as a printed circuit board, and the contacts of the device must be electrically connected to electrically conductive features of the circuit board.
Semiconductor chips are commonly provided in packages that facilitate handling of the chips during the manufacture and mounting of the chips on an external substrate, such as a circuit board or other circuit panel. Many semiconductor chips are provided in packages suitable for surface mounting. Some types of semiconductor chips have been developed using three-dimensional packaging. A three-dimensional package contains two or more integrated circuits that are stacked vertically so that they occupy less space and/or have greater connectivity. Some three-dimensional packages include through-silicon vias (TSVs) that provide vertical connections through the bodies of the integrated circuits. Typically, the TSV is filled with copper for optimized electrical performance, and the via is revealed using an etching process.
Packages that utilize TSV technology have several advantages over those that have edge wiring including, for example, a higher interconnect density and a smaller form factor. However, while TSV technology has its advantages, there are challenges. For example, the current methods of revealing vias in which copper has been deposited may result in damage to the chip because of the material properties of copper and silicon including the tendency of copper to expand more readily than silicon in response to high temperature. Since the etching process may expose the package to heat, copper components may expand more than the surrounding silicon, damaging the silicon surrounding the copper. Furthermore, copper ions may diffuse or migrate, contaminating electrically active silicon regions or dielectric films. This may damage the package, rendering it unusable.
Therefore, new devices and methods of manufacturing microelectronic packages are desirable.